1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an In-Plane Switching (IPS) mode liquid crystal display device and a method for fabricating the same.
2. Discussion of the Related Art
In general, liquid crystal display (LCD) devices use optical anisotropy and polarization properties of liquid crystal molecules due to their definite orientation order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules may be controlled by application of an electric field to the liquid crystal molecules. For example, as the alignment direction of the applied electric field changes, so does the alignment of the liquid crystal molecules. Accordingly, refraction of incident light may be controlled by the orientation of the liquid crystal molecules, thereby displaying an image onto a display panel.
Presently, active matrix liquid crystal display (LCD) devices, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are commonly used because of their high resolution and superiority for displaying moving images. In general, a liquid crystal display (LCD) device comprises a color filter substrate having a common electrode, an array substrate having a pixel electrode, and a liquid crystal material layer between the color filter substrate and the array substrate. The liquid crystal display (LCD) device drives the liquid crystal material by controlling application an electric field between the common electrode and the pixel electrode. However, since viewing angle properties of this type of liquid crystal display (LCD) device are relatively poor, new types of liquid crystal display (LCD) devices have been developed. For example, In-Plane Switching (IPS) mode liquid crystal display (LCD) devices have been developed that have superior viewing angle properties.
FIG. 1 is a plan view of an array substrate pixel for an in-plane switching (IPS) mode liquid crystal display (LCD) device according to the related art. In FIG. 1, a plurality of gate lines 12 are formed along a first direction on the substrate 10, a storage line 16 is formed along the first direction adjacent to the gate line 12 on the substrate 10, and a plurality of data lines 30 are formed along a second direction on the substrate 10. Intersections between each of the gate lines 12 and the data lines 30 defines a pixel region “P,” and a thin film transistor “T” is formed at each of the intersections of the gate lines 12 and the data lines 30. The thin film transistor “T” has a gate electrode 14, a semiconductor layer 22, a source electrode 26, and a drain electrode 28. The gate electrode 14 is connected to the gate line 12, and the source electrode 26 is connected to the data line 30. A semiconductor line 24 extends from the semiconductor layer 22 and is formed under the data line 30. A pixel electrode 36 (36a, 36b and 36c) is formed within the pixel region “P” and is connected to the drain electrode through a contact hole 34. A common electrode 18 (18a and 18b) is also formed within the pixel region “P” and is connected to the storage line 16.
The pixel electrode 36 comprises a first horizontal portion 36a, a plurality of vertical portions 36b, and a second horizontal portion 36c. The first horizontal portion extends from the drain electrode 28 and the vertical portions 36b vertically extend from the first horizontal portion 36a and are spaced apart from each other. The second horizontal portion 36c connects each of the plurality of vertical portions 36b over the storage line 16. The common electrode 18 comprises a horizontal portion 18a and a plurality of vertical portions 18b. The vertical portions 18b vertically extend from the storage line 16 and are arranged within the pixel region “P” in an alternating order with the vertical portions 36b of the pixel electrode 36. The horizontal portion 18a connects each of the plurality of vertical portions 18b. 
A storage capacitor CSt connected in parallel to the pixel electrode 36 is formed over the storage line 16. The storage capacitor CSt comprises a first storage electrode and a second storage electrode, wherein a part of the storage line 16 serves as the first storage electrode and the second horizontal portion 36c of the pixel electrode serves as the second storage electrode. In addition, a spaced region “S” is formed between the data line 30 and the vertical portion 18b of the common electrode. Accordingly, since an abnormal electric field is generated within the spaced region “S,” molecules of liquid crystal material do not function properly within a region adjacent to the spaced region “S.” Thus, light leakage may occur within the region adjacent to the spaced region “S.” Therefore, a black matrix is necessarily formed on an upper substrate (not shown) to prevent the light leakage by blocking the region adjacent to the spaced region “S”.
FIG. 2 is a cross-sectional view along II—II of FIG. 1 according to the related art. In FIG. 2, the vertical portions 18b of the common electrode are formed along both sides of the data line 30. Accordingly, the spaced regions “S” are formed between the vertical portions 18b and the data line 30, and a black matrix 42 is formed beneath the upper substrate 40. However, if there is an alignment error when the upper and the lower substrates 40 and 10 are attached together, the black matrix 42 may fail to block the entire spaced region “S,” and light leakage may occur within the spaced region “S”.
FIGS. 3A to 3E are cross-sectional views taken along a line III—III of FIG. 1 and illustrating a fabricating sequence of an array substrate according to the related art, and FIGS. 4A to 4E are cross-sectional views along IV—IV of FIG. 1, and illustrate another fabrication sequence of an array substrate according to the related art. In FIGS. 3A and 4A, a gate electrode 14, as well as the gate line 12, the storage line 16, and the horizontal and vertical portions 18a and 18b of the common electrode of FIG. 1, are formed on the substrate 10 by depositing one or two of conductive metal material, such as aluminum (Al), aluminum alloys, tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), and then patterned. Generally, a metal material having a low resistivity such as aluminum (Al) or aluminum alloys (AlNd), for example, is used for the gate electrode 14 to prevent signal delay. However, since aluminum-based metal materials are prone to chemical corrosion and have weak physical strength, chromium (Cr) or molybdenum (Mo) may first be deposited on the aluminum-based metal materials. A first insulating layer 20, commonly referred to as a gate insulating layer, is subsequently formed on an entire surface of the substrate 10 upon which the gate line 12, the storage line 16, and the vertical portion 18b of the common electrode are already formed.
FIGS. 3B and 4B show laminated structures of the array substrate after a second mask process according to the related art. A semiconductor layer 22 and a semiconductor line 24 are formed on the first insulating layer 20. The semiconductor layer 22 has an active layer 22a and an ohmic contact layer 22b formed over the gate electrode 14, and the semiconductor layer 22 extends to a data line area “DL” to form the semiconductor line 24. The active layer 22a is formed of amorphous silicon (a-Si:H), and the ohmic contact layer 22b is formed of impurity-doped amorphous silicon (n+a-Si:H).
FIG. 3C and FIG. 4C show laminated structures of the array substrate after a third mask process according to the related art. Source and drain electrodes 26 and 28 and a data line 30 are each formed on the semiconductor layer 22 by depositing one of a conductive metal material, such as aluminum (Al), aluminum alloys, tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum(Ta), and titanium (Ti), and then patterning it. The source electrodes 26 and the drain electrode 28 are spaced apart from each other and the data line 30 extends from the source electrode 26.
FIG. 3D and FIG. 4D show laminated structures of the array substrate after a fourth mask process according to the related art. A passivation layer 32 is formed on the entire surface of the substrate 10 by coating organic insulating material, such as benzocyclobutene (BCB) or acrylic resin, or by depositing inorganic insulating materials, such as silicon nitride (SiNx) or silicon oxide (SiO2). The passivation layer 32 is then patterned to form a drain contact hole 34 to expose a portion of the drain electrode 28.
FIG. 3E and FIG. 4E show laminated structures of the array substrate after a fifth mask process according to the related art. The first horizontal portion 36a, the vertical portion 36b, and the second horizontal portion 36c of the pixel electrode are formed by depositing a transparent conductive metal material, such as indium tin oxide (ITO) and indium zinc oxide (IZO), on the passivation layer 32, and then patterning it. The first horizontal portion 36a contacts the exposed portion of the drain electrode 28 and extends into the pixel region “P” (in FIG. 1). The vertical portions 36b extend from the first horizontal portion 36a and are arranged in an alternating pattern with the vertical portions 18b of the common electrode. The second horizontal portion 36c (in FIG. 1) is disposed over the storage line 16 and interconnects each of the plurality of vertical portions 36b. 
The in-plane switching (IPS) mode liquid crystal display (LCD) device fabricated using the above-described process suffers from the light leakage problem described with respect to FIG. 2. Moreover, the process for fabricating the array substrate is relatively complex, whereby production yield decreases.